The reduction of the size and the inherent features of semiconductor devices (e.g., field effect transistor (FET) devices) has enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the FET devices and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and drain of a FET device alters a resistance associated with the channel region, thereby affecting a performance of the FET device. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the FET device, which, assuming other parameters are maintained relatively constant, may allow an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the MOS device.
To further enhance the performance of FET devices, stress may be introduced in the channel region of a FET device to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type FET (“NFET”) device in a source-to-drain direction, and to induce a compressive stress in the channel region of a p-type FET (“PFET”) device in a source-to-drain direction.
A commonly used method for applying compressive stress to the channel regions of FET devices includes growing stressors in the source and drain regions. Such a method typically includes the steps of forming a gate stack on a semiconductor substrate, forming gate spacers on sidewalls of the gate stack, forming recesses in the silicon substrate along the gate spacers, and epitaxially growing stressors in the recesses. Since the stressors have a lattice constant different from that of silicon, it expands and applies a stress to the channel region, which is located between a source stressor and a drain stressor.
The above-discussed method is affected by pattern-loading effects, which occur due to a difference in pattern densities. The pattern-loading effects pertain to a phenomenon occurring upon simultaneous etching of a semiconductor substrate in a region of a higher pattern density and a region of a lower pattern density. The profiles of the trenches are related to the density of patterns.